This invention relates to a grounded emitter, push-pull, transistor circuit, and particularly to such a circuit which completely eliminates the deleterious effects of minority carrier storage time even when the two transistors are alternately driven by a high-frequency input signal.
In recent years, in order to meet the handling convenience requirements of transistor push-pull circuits, and to cope with the space limitations imposed by the environments in which such circuits are used, efforts have been continuously and diligently made to reduce the size of push-pull circuits. One of the best and most effective ways to reduce the size of a push-pull switching circuit is to control the transistors used therein with a high-frequency input signal. The use of a high-frequency input signal makes it possible to utilize very small transformers, and correspondingly small choke-coils and condensors for smoothing voltage amplitude fluctuations.
When a high-frequency input signal is fed to the base electrodes of the push-pull transistors, however, there is a brief period during which the two transistors conduct simultaneously, i.e. one transistor is driven into a conducting state while the other transistor still remains conducting due to minority carrier storage. Such simultaneous conduction causes heavy currents to flow through the collector-emitter paths of the transistors, resulting in the deterioration and possible destruction of the transistors.
Minority carrier storage is caused by the accumulation of minority carriers in the base region when a transistor is driven in saturation.
To overcome the deleterious effects of such storage time, a circuit configuration as shown in FIG. 1 (taken from U.S. Pat. No. 3,421,099) has been proposed. With such a circuit configuration, however, the storage time problem cannot be completely eliminated. Referring to FIG. 1, a (lower) feedback path 42 derived from a feedback winding 44 is used to prevent an input signal from being fed to the base of a transistor 41 while the other transistor 40 is still conducting due to the minority carrier storage effect. A large number of turns in winding 44 is necessary, however, to bias the base of transistor 41 sufficiently negative to keep it cutoff even when an input signal is applied to its base. Consequently, heavy power losses result due to energy dissipated in the diode 48, the resistor 40, and the winding 44.
If the number of turns in winding 44 is decreased, however, the negative bias becomes insufficient and transistor 41 begins to conduct while transistor 40 is still conducting, due to the storage time effect. Thus, there is a time during which both transistors conduct simultaneously. When this occurs the magnetic fluxes generated in the transformer 28 by the currents flowing through the transistors 40 and 41 cancel each other, which reduces the collector loads to just the resistance of the primary winding. As a result, heavy collector currents flow through the transistors, which causes excessive power dissipation in them, and in some cases, their complete destruction.